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IS41LV32256
256K x 32 (8-Mbit) EDO DYNAMIC RAM 3.3V, 100/83/66 MHz
FEATURES
* 262,144-word by 32-bit organization * Single +3.3V 0.3V power supply * Four CAS inputs for Byte Write and Byte Read control * Refresh modes: RAS-Only, CAS-Before-RAS (CBR), and Hidden * 512-cycle refresh in 8 ms * Fast Page Mode with Extended Data Out * 100-pin PQFP, TQFP package
ISSI
SEPTEMBER 2000
(R)
DESCRIPTION The ISSI IS41LV32256 is organized in a 262,122 x 32-bit
CMOS Dynamic Random Access Memory. Four CAS signals facilitate execution of Byte Read and Byte Write operations. A very fast EDO cycle time of 10 ns allows an operating frequency of 100 MHz and makes the IS41LV32256 an ideal frame buffer memory for graphics applications. The IS41LV32256 is compatible with JEDEC standard SGRAMs. This 8-Mbit EDO memory offers a significantly lower latency and a faster memory cycle than the SGRAM. ISSI's IS41LV32256 3.3V 256K x 32 device is pin/voltage compatible with all standard SGRAM parts. The IS41LV32256 is available in a 100-pin PQFP and TQFP package.
KEY TIMING PARAMETERS
Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Max. OE Access Time (tOE) Min. Read/Write Cycle Time (tRC) Min. EDO Cycle Time (tPC) -28 28 9 15 9 48 12 -30 30 9 16 9 53 12 -35 35 10 18 10 60 15 Unit ns ns ns ns ns ns
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
1
IS41LV32256
FUNCTIONAL BLOCK DIAGRAM
OE CLOCK GENERATOR
ISSI
(R)
OE
WE
WE CLOCK GENERATOR Data I/O Buffers I/O0-31
CAS0 CAS1 CAS2 CAS3
CAS CLOCK GENERATOR AY0-AY8 COLUMN DECODERS
A0-A8
CONTROLS
SENSE AMPLIFIERS 512 x 32
AX0-AX8
ROW DECODERS
512
MEMORY ARRAY 256K x 32
RAS
RAS CLOCK GENERATOR
2
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
IS41LV32256
PIN CONFIGURATIONS
100-Pin PQFP, TQFP
I/O31 I/O30 I/O29 GND GND GND I/O2 I/O1 I/O0 Vcc NC NC NC NC NC NC NC NC NC NC
ISSI
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O28 Vcc I/O27 I/O26 GND I/O25 I/O24 Vcc I/O15 I/O14 GND I/O13 I/O12 Vcc GND Vcc I/O11 I/O10 GND I/O9 I/O8 Vcc NC CAS3 CAS1 NC NC OE NC A8
(R)
I/O3 Vcc I/O4 I/O5 GND I/O6 I/O7 Vcc I/O16 I/O17 GND I/O18 I/O19 Vcc Vcc GND I/O20 I/O21 GND I/O22 I/O23 Vcc CAS0 CAS2 WE NC NC RAS NC NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 A5
49 A6
A0
A1
A2
A3
GND
A4
NC
NC
NC
NC
NC
NC
NC
NC
NC
PIN DESCRIPTIONS
A0-A8 RAS CAS0 CAS1 CAS2 CAS3 WE OE I/O0-I/O31 Vcc GND NC Address Inputs Row Address Strobe Column Address Strobe for First Byte (I/O0-I/O7) Column Address Strobe for Second Byte (I/O8-I/O15) Column Address Strobe for Third Byte (I/O16-I/O23) Column Address Strobe for Fourth Byte (I/O24-I/O31) Write Enable Output Enable Data Inputs/Outputs +3.3V Supply Ground No Connection: This pin should be left unconnected or tied to ground.
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
Vcc
NC
A7
50
3
IS41LV32256
TRUTH TABLE
Function Standby Read: Double Word Read: 1st Byte Read: 2nd Byte RAS CAS0 CAS1 CAS2 CAS3 WE H L L L H L L H H L H L H L H H H L H H X H H H OE X L L L Address X ROW/COL ROW/COL ROW/COL
ISSI
I/O High-Z DOUT I/O0-7=DOUT; I/O8-31=High-Z I/O0-7=High-Z; I/O8-15=DOUT; I/O16-31=High-Z I/O0-15=High-Z; I/O16-23=DOUT; I/O24-31=High-Z I/O0-23=High-Z; I/O24-31=DOUT DIN I/O0-7=DIN; I/O8-31=X I/O0-8=X; I/O8-15=DIN; I/O16-31=X I/O0-15=X; I/O16-23=DIN; I/O24-31=X I/O0-23=X; I/O24-31=DIN DOUTDIN DOUT DOUT DOUT DOUT DIN DIN DOUTDIN DOUTDIN DOUT DINHigh-Z High-Z High-Z
(R)
Read: 3rd Byte
L
H
H
L
H
H
L
ROW/COL
Read: 4th Byte Write: Double Word (Early) Write: 1st Byte (Early) Write: 2nd Byte (Early)
L L L L
H L L H
H L H L
H L H H
L L H H
H L L L
L X X X
ROW/COL ROW/COL ROW/COL ROW/COL
Write: 3rd Byte (Early)
L
H
H
L
H
L
X
ROW/COL
Write: 4th Byte (Early)
L
H
H L HL HL HL HL HL HL HL HL L L H L
H L HL HL HL HL HL HL HL HL L L H L
L
L
X
ROW/COL ROW/COL ROW/COL COL ROW/COL COL ROW/COL COL ROW/COL COL ROW/COL ROW/COL ROW X
Read-Write(1,2) L L (2) Fast-Page-Mode Read: EDO 1st Cycle: L HL Subsequent Cycles: L HL Fast-Page-Mode Read: High-Z(2) 1st Cycle: L HL Subsequent Cycles: L HL Fast-Page-Mode Write: (Early)(1) 1st Cycle: L HL Subsequent Cycles: L HL Fast-Page-Mode Read-Write(1,2) 1st Cycle: L HL Subsequent Cycles: L HL Hidden Refresh Read(2) LHL L (1) Hidden Refresh Write LHL L RAS-Only Refresh L H (3) CBR Refresh HL L
L HL LH HL H L HL H L HL H HL HL H HL HL L X HL L X HL HL LH HL HL LH L H L L L X H X X L X X
Notes: 1. BYTE WRITE may be executed with CAS0, CAS1, CAS2 or CAS3 active. 2. BYTE READ may be executed with CAS0, CAS1, CAS2 or CAS3 active. 3. Only one CAS signal (CAS0, CAS1, CAS2 or CAS3) must be active.
4
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
IS41LV32256
ISSI
(R)
POWER-ON
The initial application of the VCC supply requires a 200-s wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol tA tSTG VT IOUT PD Parameters Ambient Temperature Under Bias Storage Temperature Voltage Relative to GND Data Output Current Power Dissipation Rating -1.0 to +80 -50 to +125 -1.0 to +5.5 50 1.0 Unit C C V mA W
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS(1) (TA = 0C to 70C)
Symbol VCC VIH VIL Parameter Power Supply Input High Voltage Input Low Voltage Min. 3.0 2.4 -0.5 Typ. 3.3 -- -- Max. 3.6 VCC + 0.5 0.4 Unit V V V
Note: 1. Voltages are referenced to GND.
CAPACITANCE(1,2)
Symbol CIN CIO Parameter Input Capacitance Data Input/Output Capacitance Max. 5 7 Unit pF pF
Notes: 1. Capacitance is sampled and 100% tested. 2. Test conditions: TA = 25C, f = 1 MHz, VCC = 3.3V.
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
5
IS41LV32256
DC CHARACTERISTICS (TA = 0C to 70C, VCC = 3.3V 0.3V)
Symbol VIH VIL VOH VOL ILI ILO ICC1 ICC2 Icc3 ICC4 ICC5 ICC6 Parameter Input HIGH (Logic 1) Voltage, All Inputs Input LOW (Logic 1) Voltage, All Inputs Output HIGH Voltage Output LOW Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating)(2,3,15,16) Power Supply Current (Standby) Average Power Supply Current (RAS-Only Refresh)(2,3,15,16) Average Power Supply Current (Fast Page Mode)(2,3,15,18) Average Power Supply Current (CAS-before-RAS Refresh)(2,3,15.16) CMOS Standby Current Condition -28 Min. Max. -30 Min. Max. 2.0 Vcc + 0.5 -0.5 0.8 2.4 Vcc 0 0.4 -10 10 -10 10 -- -- -- -- -- -- 250 2.5 250 230 250 600
ISSI
-35 Min. Max. 2.0 Vcc + 0.5 -0.5 0.8 2.4 Vcc 0 0.4 -10 10 -10 10 -- -- -- -- -- -- 240 2.5 240 220 240 600 Units V V V V A A mA mA mA mA mA A -- 2.0 Vcc + 0.5 -- -0.5 0.8 IOH = -2 mA 2.4 Vcc IOL = 2 mA 0 0.4 0V < VIN < VCC -10 10 0V < VOUT < 3.6V; -10 10 Output Disable RAS, CAS Cycling; -- 250 tRC = Min. RAS, CAS = VIH -- 2.5 RAS = Cycling; -- 250 CAS = VIH; tRC = Min. RAS = VIL; -- 230 CAS = Cycling; tPC = Min. RAS = Cycling; -- 250 CAS-before-RAS RAS, CAS = VCC -0.2V -- 600
(R)
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.)
-28 Symbol tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR tRAD tRAL tRPC tRSH Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(26) CAS Precharge Time(9, 25) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) Min. 48 -- -- -- 28 17 5 5 28 10 0 6 0 5 21 8 15 0 7 Max. -- 28 9 15 10K -- 10K -- -- 19 -- -- -- -- -- 13 -- -- -- Min. 53 -- -- -- 30 18 5 5 30 10 0 6 0 5 22 8 16 0 7 -30 Max. -- 30 9 16 10K -- 10K -- -- 21 -- -- -- -- -- 15 -- -- -- Min. 60 -- -- -- 35 20 6 5 35 11 0 7 0 6 25 9 18 0 8 -35 Max. -- 35 10 18 10K -- 10K -- -- 28 -- -- -- -- -- 16 -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Continued)
Rev. A 09/29/00
6
Integrated Silicon Solution, Inc.
IS41LV32256
ISSI
-28 -30 Max. -- -- 15 9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100K 17 -- -- 7 10 Min. 3 5 3 -- 10 10 5 0 0 0 5 22 5 10 7 5 0 22 15 5 0 5 73 40 18 25 12 30 -- 35 3 3 3 Max. -- -- 15 9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100K 18 -- -- 7 10 Min. 3 5 3 -- 10 10 5 0 0 0 5 24 6 10 8 8 0 24 15 6 0 6 80 45 20 30 15 35 -- 40 3 3 3 -35 Max. -- -- 15 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100K 21 -- -- 15 15 Min. 3 5 3 -- 10 10 5 0 0 0 5 21 5 10 7 5 0 21 15 5 0 5 73 40 18 24 12 28 -- 34 3 3 3
(R)
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.)
Symbol tCLZ tCRP tOD tOE tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWP tWPZ tRWL tCWL tWCS tDHR tACH tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tCHO tOFF tWHZ Parameter CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21) Output Disable Time(19, 28, 29) Output Enable Time(15, 16) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) EDO Page Mode READ or WRITE Cycle Time(24) RAS Pulse Width in EDO Page Mode Access Time from CAS Precharge(15) EDO Page Mode READ-WRITE Cycle Time(24) Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Output Disable Delay from WE Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Continued)
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
7
IS41LV32256
ISSI
-28 -30 Max. -- -- -- -- 8 50 Min. 10 5 7 0 -- 1 Max. -- -- -- -- 8 50 Min. 10 8 8 0 -- 1 -35 Max. -- -- -- -- 8 50 Min. 10 5 7 0 -- 1 ns ns ns ms ns
(R)
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.)
Symbol tCLCH tCSR tCHR tORD tREF tT Parameter Last CAS going LOW to First CAS returning HIGH(23) CAS Setup Time (CBR REFRESH)(30, 20) CAS Hold Time (CBR REFRESH)(30, 21) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Refresh Period (512 Cycles) Transition Time (Rise or Fall)(2, 3) Units ns
Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD * tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS * tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD * tRWD (MIN), tAWD * tAWD (MIN) and tCWD * tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first CAS edge to transition LOW. 21. The last CAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling CAS edge to first rising CAS edge. 24. Last rising CAS edge to next cycle's last rising CAS edge. 25. Last rising CAS edge to first falling CAS edge. 26. Each CAS must meet minimum pulse width. 27. Last CAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters.
8
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
IS41LV32256
READ CYCLE (Outputs Controlled by RAS)
ISSI
tRC tRAS tRP
(R)
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH tRRH
CAS0-CAS3
tAR tASR tRAD tRAH tRAL tASC tCAH
ADDRESS WE
Row
tRCS
Column
tRCH
Row
tAA tRAC tCAC tCLC tOFF(1)
I/O
Open
tOE
Valid Data
tOD
Open
OE
tOES
Don't Care
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
9
IS41LV32256
READ CYCLE (Outputs Controlled by CAS)
tRC tRAS tRP
ISSI
(R)
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH tRRH
CAS0-CAS3
tAR tASR tRAD tRAH tRAL tASC tCAH
ADDRESS WE
Row
tRCS
Column
tRCH
Row
tAA tRAC tCAC tCLC
tOFF(1)
I/O
Open
tOE
Valid Data
tOD
Open
OE
tOES
Don't Care
10
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
IS41LV32256
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC tRAS tRP
ISSI
(R)
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH
CAS0-CAS3
tAR tASR tRAD tRAH tASC tRAL tCAH tACH
ADDRESS
Row
Column
tCWL tRWL tWCR tWCS tWCH tWP
Row
WE
tDHR tDS tDH
I/O
Valid Data
Don't Care
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
11
IS41LV32256
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
ISSI
tRWC tRAS tRP
(R)
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH
CAS0-CAS3
tAR tASR tRAD tRAH tRAL tASC tCAH tACH
ADDRESS
Row
tRCS
Column
tRWD tCWD tAWD
Row
tCWL tRWL tWP
WE
tAA tRAC tCAC tCLZ tDS tDH
I/O
Open
tOE
Valid DOUT
tOD
Valid DIN
Open
tOEH
OE
Undefined Don't Care
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Integrated Silicon Solution, Inc.
Rev. A 09/29/00
IS41LV32256
EDO-PAGE-MODE READ CYCLE
ISSI
tRASP tRP
(R)
RAS
tCSH tCRP tRCD tCAS, tCLCH tCP tPC(1) tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP
CAS0-CAS3
tAR tRAD tASR tASC tCAH tASC tCAH tASC tRAL tCAH
ADDRESS
Row
tRAH tRCS
Column
Column
Column
tRCH
Row
tRRH
WE
tAA tRAC tCAC tCLZ tCAC tCOH tAA tCPA tCAC tCLZ tAA tCPA tOFF
I/O
Open
tOE tOES
Valid Data
Valid Data
tOEHC tOD tOES
Valid Data
tOE
Open
tOD
OE
tOEP
Undefined Don't Care
Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
13
IS41LV32256
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
ISSI
tRP tCSH tPC tCAS, tCLCH tCP tCAS, tCLCH tCP tRSH tCAS, tCLCH tACH tRAL tCAH
(R)
RAS
tCRP tRCD tCP
CAS0-CAS3
tAR tRAD tASR tASC tACH tCAH tASC tACH tCAH tASC
ADDRESS
Row
tRAH
Column
tCWL tWCS tWCH tWP
Column
tCWL tWCS tWCH tWP
Column
tCWL tWCS tWCH tWP
Row
WE
tWCR tDHR tDS tDH tRWL tDS tDH tDS tDH
I/O OE
Valid Data
Valid Data
Valid Data
Don't Care
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Integrated Silicon Solution, Inc.
Rev. A 09/29/00
IS41LV32256
ISSI
tRASP tRP tCSH tPC / tPRWC(1) tCAS, tCLCH tRSH tCAS, tCLCH
(R)
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
RAS
tCRP tRCD tCAS, tCLCH tCP tCP tCP
CAS0-CAS3
tASR tRAH tAR tRAD tASC tRAL tCAH
tCAH
tASC
tCAH
tASC
ADDRESS
Row
tRWD tRCS
Column
tCWL tWP tAWD tCWD
Column
tCWL tWP tAWD tCWD
Column
tRWL tCWL tWP tAWD tCWD
Row
WE
tAA tRAC tCAC tCLZ tDH tDS tAA tCPA tCAC tCLZ tDH tDS tAA tCPA tCAC tCLZ tDH tDS
I/O
Open
tOE
DOUT
DIN
tOD tOE
DOUT
DIN
tOD tOE
DOUT
DIN
tOD tOEH
Open
OE
Undefined Don't Care
Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
15
IS41LV32256
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
ISSI
tRASP tRP
(R)
RAS
tCSH tPC tCRP tRCD tCAS tCP tCAS tPC tCP tRSH tCAS tCP
CAS0-CAS3
tASR tRAH tAR tRAD tASC tACH tRAL tCAH
tCAH
tASC
tCAH
tASC
ADDRESS
Row
tRCS
Column (A)
Column (B)
tRCH tWCS
Column (N)
tWCH
Row
WE
tAA tRAC tCAC tCPA tCAC tCOH tAA tWHZ tDS tDH
I/O
Open
tOE
Valid Data (A)
Valid Data (B)
DIN
Open
OE
Don't Care
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Integrated Silicon Solution, Inc.
Rev. A 09/29/00
IS41LV32256
AC WAVEFORMS READ CYCLE (With WE-Controlled Disable)
RAS
tCSH tCRP tRCD tCAS tCP
ISSI
(R)
CAS0-CAS3
tAR tASR tRAD tRAH tASC tCAH tASC
ADDRESS WE
Row
tRCS
Column
tRCH tRCS
Column
tAA tRAC tCAC tCLZ
tWHZ
tCLZ
I/O
Open
tOE
Valid Data
Open
tOD
OE
Undefined Don't Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC tRAS tRP
RAS
tCRP tRPC
CAS0-CAS3
tASR tRAH
ADDRESS I/O
Row Open
Row
Don't Care
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
17
IS41LV32256
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
ISSI
tRP tRAS tRP tRAS
(R)
RAS
tRPC tCP tCHR tCSR tRPC tCSR tCHR
CAS0-CAS3 I/O Open
HIDDEN REFRESH CYCLE (WE = HIGH; OE = LOW)(1)
tRAS tRP tRAS
RAS
tCRP tRCD tRSH tCHR
CAS0-CAS3
tAR tASR tRAD tRAH tASC tRAL tCAH
ADDRESS
Row
Column
tAA tRAC tCAC tCLZ tOFF(2)
I/O
Open
tOE tORD
Valid Data
Open
tOD
OE
Undefined Don't Care
Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
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Integrated Silicon Solution, Inc.
Rev. A 09/29/00
IS41LV32256
ORDERING INFORMATION Commercial Range: 0C to 70C
Speed (ns) 28 30 35 Order Part No. IS41LV32256-28PQ IS41LV32256-28TQ IS41LV32256-30PQ IS41LV32256-30TQ IS41LV32256-35PQ IS41LV32256-35TQ Package PQFP TQFP PQFP TQFP PQFP TQFP
ISSI
(R)
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
Integrated Silicon Solution, Inc.
Rev. A 09/29/00
19

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